1. Field of the Invention
2. Description of the Related Art
The present invention generally relates to DC burn-in that is used to keep the wordlines at a very high voltage over a period of about 10s so as to place maximum stress on an isolation between wordlines and cells or bitlines.
This maximum stress condition is used in place of normal operations (e.g., individual reading and writing) through each wordline to reduce the testing time. A normal operating condition cannot be realistically used to test a circuit since the testing time would be excessive. For example, for 2 k over 5 hours of testing time would be necessary to individually hold every word line high for 10s using normal operating conditions.
Therefore, conventionally all wordlines are simultaneously activated at the same time to produce the maximum stress and reduce the time duration of burn-in. However, switching all lines on at the same time leads to a huge voltage drop in the wordline power network (Vpp net). More specifically, turning all the wordlines on at once induces a huge current spike on the wordline power supply and can lead to a voltage drop in the power net and to reliability problems at the power lines. More specifically, if an external voltage supply Vpp is used to power the conventional bum-in, the resistance of the on-chip wiring from the external pad to the internal Vpp net limits the current. Therefore, the wire from the pad to the Vpp net will see significant electro-migration stress and might even fuse.
An exemplary conventional circuit is illustrated in FIG. 1. The conventional circuit includes address receivers 10 which receive addresses 15, control signal receiver 14, a test mode decoder 11, a word decode system 12 supplied with a wordline power network voltage 17 (Vpp) and a memory array 13 which receives a DC burn-in signal 16 from the test mode decoder 11.
FIG. 2 illustrates the timing of the signals within the circuit shown in FIG. 1. More specifically, FIG. 2 illustrates the row address strobe signal (RAS), column address strobe signal (CAS), write enable signal (WE), address signal (ADR--which can be any of addresses XA.sub.o . . . XA.sub.n), word line signals (WL0, WL . . . WL.sub.x and wordline power network voltage signal. (Vpp)
As shown in FIG. 2, the DC burn-in signal causes all the word lines (WL0, WL . . . WL.sub.x) to simultaneously go high, which causes a current spike and a substantial drop (e.g., greater than 2 V) on the wordline power network voltage signal Vpp. As mentioned above, this current spike on the wordline power supply can lead to reliability problems at the power lines.